SPO600 – Conclusion

Unfortunately I was unable to finish the packages I chose too look into for this course(mpich, and blender). It was much too early to start trying to port blender, and mpich continued to have problems through the course.

Final Stage of Mpich:
For mpich, I was able to both configure, and compile it on x86_64, and aarch64. For x86_64 all the tests ran successfully. However on aarch64(qemu) all the tests continually failed, this was because qemu could not emulate the network interfaces.

I moved to the foundation model, and started a configure and compile, 20 hours later… it was complete. When running the tests I ran into multiple issues, first, all the tests would time out, even if the timeout was increased. Second, all the perl scripts that were being run did not have “shebang” lines for perl, and failed. After adding in the lines, they continued to have different errors, and exited with errors.

Compiling on qemu did not take so long, but running them on the foundation model took almost a whole day. The commands used for configuring, compiling, and testing:

# This command disables the fortran compiler from being used, as it is currently not in aarch64
time ./configure --disable-f77 --disable-fc --with-atomic-primitive
real    22m37.044s
user    20m22.424s
sys     3m8.911s

time make
real    74m34.936s
user    72m9.635s
sys     2m1.169s

# Testing did not work on aarch64, no matter how long you wait, it always timed out(on foundation model). Qemu failed immediately with errors.
time make testing

Finally I moved on, and stopped trying to test the program, instead started finding all the functions that needed to be ported to aarc64. Found files that had lists of atomic functions that need to be ported for each architecture:

   static _opa_inline int   OPA_load_int(_opa_const OPA_int_t *ptr);
   static _opa_inline void  OPA_store_int(OPA_int_t *ptr, int val);
   static _opa_inline void *OPA_load_ptr(_opa_const OPA_ptr_t *ptr);
   static _opa_inline void  OPA_store_ptr(OPA_ptr_t *ptr, void *val);

   static _opa_inline void OPA_add_int(OPA_int_t *ptr, int val);
   static _opa_inline void OPA_incr_int(OPA_int_t *ptr);
   static _opa_inline void OPA_decr_int(OPA_int_t *ptr);

   static _opa_inline int OPA_decr_and_test_int(OPA_int_t *ptr);
   static _opa_inline int OPA_fetch_and_add_int(OPA_int_t *ptr, int val);
   static _opa_inline int OPA_fetch_and_incr_int(OPA_int_t *ptr);
   static _opa_inline int OPA_fetch_and_decr_int(OPA_int_t *ptr);

   static _opa_inline void *OPA_cas_ptr(OPA_ptr_t *ptr, void *oldv, void *newv);
   static _opa_inline int   OPA_cas_int(OPA_int_t *ptr, int oldv, int newv);

   static _opa_inline void *OPA_swap_ptr(OPA_ptr_t *ptr, void *val);
   static _opa_inline int   OPA_swap_int(OPA_int_t *ptr, int val);

   (the memory barriers may be macros instead of inline functions)
   static _opa_inline void OPA_write_barrier();
   static _opa_inline void OPA_read_barrier();
   static _opa_inline void OPA_read_write_barrier();

   Loads and stores with memory ordering guarantees (also may be macros):
   static _opa_inline int   OPA_load_acquire_int(_opa_const OPA_int_t *ptr);
   static _opa_inline void  OPA_store_release_int(OPA_int_t *ptr, int val);
   static _opa_inline void *OPA_load_acquire_ptr(_opa_const OPA_ptr_t *ptr);
   static _opa_inline void  OPA_store_release_ptr(OPA_ptr_t *ptr, void *val);

   static _opa_inline void OPA_compiler_barrier();

Aarch64 should be able to use memory barriers similar to other arm architectures since dmb and dsb are both in aarch64 instruction set:

#define OPA_arm_dmb_() __asm__ __volatile__  ( "dmb" ::: "memory" )
#define OPA_arm_dsb_() __asm__ __volatile__  ( "dsb" ::: "memory" )

#define OPA_write_barrier()      OPA_arm_dsb_()
#define OPA_read_barrier()       OPA_arm_dmb_()
#define OPA_read_write_barrier() OPA_arm_dsb_()
#define OPA_compiler_barrier()   __asm__ __volatile__  ( "" ::: "memory" )

Many of the atomic functions could be ported the same way for each of the architectures:

/* Aligned loads and stores are atomic. */
static _opa_inline int OPA_load_int(_opa_const OPA_int_t *ptr)
        return ptr->v;

/* Aligned loads and stores are atomic. */
static _opa_inline void OPA_store_int(OPA_int_t *ptr, int val)
        ptr->v = val;

/* Aligned loads and stores are atomic. */
static _opa_inline void *OPA_load_ptr(_opa_const OPA_ptr_t *ptr)
        return ptr->v;

/* Aligned loads and stores are atomic. */
static _opa_inline void OPA_store_ptr(OPA_ptr_t *ptr, void *val)
        ptr->v = val;

Many other functions that are suppose to be ported, that have already been ported to armv7 seem like they will work on aarch64 as well:

static _opa_inline int   OPA_load_acquire_int(_opa_const OPA_int_t *ptr)
    int tmp;
    tmp = ptr->v;
    return tmp;
static _opa_inline void *OPA_load_acquire_ptr(_opa_const OPA_ptr_t *ptr)
        void *tmp;
        tmp = ptr->v;
        return tmp;
static _opa_inline void  OPA_store_release_ptr(OPA_ptr_t *ptr, void *val)
            ptr->v = val;

Most of the remaining functions on the list actually require some assembly inside them for load-link/store-conditional primitives. I did not get a chance to look further into these functions, they will need to be ported over to aarch64. Here are a couple examples of the armv7 LL/SC primitive functions:
static _opa_inline int OPA_LL_int(OPA_int_t *ptr)
    int val;
    __asm__ __volatile__ ("ldrex %0,[%1]"
                          : "=&r" (val)
                          : "r" (&ptr->v)
                          : "cc");

    return val;

/* Returns non-zero if the store was successful, zero otherwise. */
static _opa_inline int OPA_SC_int(OPA_int_t *ptr, int val)
    int ret; /* will be overwritten by strex */
      strex returns 0 on success
    __asm__ __volatile__ ("strex %0, %1, [%2]\n"
                          : "=&r" (ret)
                          : "r" (val), "r"(&ptr->v)
                          : "cc", "memory");

    return !ret;

About oatleywillisa

Computer Networking Student
This entry was posted in SBR600 and tagged , , , , , , , , . Bookmark the permalink.

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